Fitting more transistors onto a single die is desirable to reduce cost of electronics and improve their functional capability. A common strategy employed by semiconductor manufacturers is to simply reduce gate size of a field effect transistor (FET), and proportionally shrink area of the transistor source, drain, and required interconnects between transistors. However, a simple proportional shrink is not always possible because of what are known as “short channel effects.” Short channel effects are particularly acute when channel length under a transistor gate is comparable in magnitude to depletion depth of an operating transistor, and can include reduction in threshold voltage, severe surface scattering, drain induced barrier lowering (DIBL), source/drain punch through, and electron mobility issues.
Conventional approaches to mitigating some short channel effects can involve implantation of pocket or halo implants around the source and the drain. Halo implants can be symmetrical or asymmetrical with respect to a transistor source and drain, and typically provide a smoother dopant gradient between a transistor well and the source and drains. Unfortunately, while such implants improve some electrical characteristics such as threshold voltage rolloff and drain induced barrier lowering, the resultant increased channel doping can adversely affect electron mobility and reduce channel transconductance, primarily because of the increased dopant scattering in the channel.
Many semiconductor manufacturers have attempted to reduce short channel effects by employing new transistor types, including fully or partially depleted silicon on insulator (SOI) transistors. SOI transistors are built on a thin layer of silicon that overlies an insulator layer, have an undoped or low doped channel that minimizes short channel effects, and do not require deep well implants for operation. Unfortunately, creating a suitable insulator layer is expensive and difficult to accomplish. Modern SOI technology can use silicon wafers, but tends to require expensive and time consuming additional wafer processing steps to make an insulative silicon oxide layer that extends across the entire wafer below a surface layer of device-quality single-crystal silicon.
One common approach to making such a silicon oxide layer on a silicon wafer involves high dose ion implantation of oxygen and high temperature annealing to form a buried oxide (BOX) layer in a bulk silicon wafer. Alternatively, SOI wafers can be fabricated by bonding a silicon wafer to another silicon wafer (a “handle” wafer) that has an oxide layer on its surface. Both BOX formation and layer transfer, however, tend to be costly manufacturing techniques with a relatively high failure rate. Accordingly, manufacture of SOI transistors is not an economically attractive solution for many leading manufacturers. Factors including cost of transistor redesign to cope with “floating body” effects, the need to develop new SOI specific transistor processes, and other circuit changes is added to SOI wafer costs, render these solutions undesirable in many situations.
Another possible advanced transistor that has been investigated uses multiple gate transistors that, like SOI transistors, minimize short channel effects by having little or no doping in the channel. Commonly known as a finFET (due to a fin-like shaped channel partially surrounded by gates), use of finFET transistors has been proposed for transistors having 28 nanometer or lower transistor gate size. But again, like SOI transistors, while moving to a radically new transistor architecture solves some short channel effect issues, it creates others, often requiring even more significant transistor layout redesign than SOI. Considering the likely need for complex non-planar transistor manufacturing techniques to make a finFET, and the unknown difficulty in creating a new process flow for finFET, manufacturers have been reluctant to invest in semiconductor fabrication facilities capable of making finFETs.
Deeply depleted channel (DDC) transistors that include both a substantially undoped channel and a highly doped, deeply buried, “screening” layer that sets depletion depth of an operating transistor have potential as a cost effective and manufacturable alternative to SOI and finFET transistors. As compared to conventional transistors that use heavily doped channels, the use of an undoped channel can substantially reduce variations in threshold voltage attributable to random dopant fluctuations in the channel. The tight control of threshold voltage variation can also enable transistor designers to reduce transistor operating voltage and/or create transistors that either switch quickly (low threshold voltage transistors) or save power (high threshold voltage transistors) while switching somewhat slower. Unlike SOI transistors, DDC transistor structures and processes tend not to require a BOX or other insulating layer below the channel to have a tight control of threshold voltage; and unlike finFETs, DDC transistors tend not to require an extensive redesign of circuit layout for operation. DDC transistors are described more fully in the following patent applications, owned by Suvolta, Inc., the assignee of this patent application, and incorporated by reference in their entireties: application Ser. No. 12/708,497 entitled “Electronic Devices and Systems, and Methods for Making and Using the Same”; Appl. No. 61/323,255, entitled “Low Power Transistors, Systems, and Process Improvements”; and Appl. No. 61/357,492 entitled. “Diverse and Low Power Transistors, Systems, and Process improvements.”
Threshold voltage control, as well as efficient operation of DDC transistors, can require careful attention to undoped channel characteristics, including channel length, depth, and dopant gradient at source/drain contacts with the channel. Unfortunately, traditional techniques for controlling channel spacing and reducing short channel effects can require source/drain extensions (typically formed by out-diffusion under gate spacers) or halo implants to reduce source/drain junction gradients. Source/drain extensions (also known as lightly doped drains—“LDDs”) may be created to slightly reduce channel length by extending the source/drain toward each other using low-energy dopant implants of the same dopant type as the source and drain. Halo implants may be created by high angle implants of counterdopants around the source/drain that help prevent overexpansion of the drain depletion region into the transistor channel. Unfortunately, both conventional source/drain extensions and halo implants can cause contamination of a channel with unwanted dopants, reducing or destroying the advantages of the undoped channel or transistors with DDC structures.
The problem of channel dopant contamination can become even more acute when die supporting multiple transistor types or requiring multiple implants are implicated. Multiple implants increase the likelihood of dopant diffusion into the channel, with each implant becoming a potential source of channel contamination. In addition, each separate source/drain extension, and halo implant process step can cause silicon erosion of the substrate layer due to a cleaning (ashing) step, and can risks damage to transistor gate dielectric corners due to lateral oxidation. In “system on a chip,” microprocessor, or mixed signal processors, as well as many other advanced devices such as memory, FPGA, or analog/digital sensors, dozens of separate source/drain extensions and halo implants are often used in every die, with each implant process step introducing more dopant contaminants, slightly degrading the transistor gate structure, and increasing the risk of transistor failure. Even simple time delays between source/drain extensions and halo implant process steps can cause increased exposure of the gate dielectric layers to oxidation that damages the gate dielectric. While use of silicon nitride “L”-shaped spacers has been suggested to protect gate dielectrics from lateral oxidation “corner” attack during the multiple source/drain extensions and halo implant process steps, the space required to form L spacers typically reduces inter-transistor spacing, and complicates other processing steps such as growth or placement of tensile films or source/drain strain implants.